With the advancement of the circuit's design, a high speed and low power circuit application is particularly needed and the dimension of metal oxide semiconductor devices has to be scaled down to sub-0.1 micron meters. Shrinking the dimension of the device could produce some problems, such as a punchthrough issue and a short channel effect, which limit the shrinkage of the size of device. In IEDM Tech. Dig. page 131 on 1993, K. F. Lee et al. tried some approaches to design a complementary metal oxide semiconductor (CMOS) on bulk silicon substrate with 11.8 picoseconds gate delay. The authors of this paper summarized some design outline for improving device's operating speed. The design outlines comprise a vertical-doping-engineered transistor structures, high energy well implants for reducing junction capacitance, lateral local doping structures in the channel region of devices, two-step sidewalls and salicidation of a device's gate. By using the design outlines, the authors of the paper fabricated a CMOS structure with a shorter gate delay at room temperature than a conventional CMOS device.
To solve the punchthrough problem, the substrate doping level must be increased, which will cause a higher parasitic source-drain junction capacitance and a lower junction breakdown voltage. High energy self-aligned punchthrough implant or low energy ion channeling implant to form self-aligned counter-doped wells could be used to reduce the junction capacitance for high speed ULSI devices.
In the 0.1 micron meters regime, masking the punchthrough implant from the source-drain region and using lateral punchthrough implants are used to reduce the parasitic source-drain capacitance. A simulation study for a novel self-aligned punchthrough implant is published in IEEE Trans. Electron Devices, on page 1312 of vol. ED-43 on 1996, entitled "A Novel Self-Aligned Punchthrough Implant: A Simulation Study". The paper presents a simulation study of a novel self-aligned punchthrough implant. In this paper, a process for a novel and simple self-aligned punchthrough implant is presented. The self-aligned dopant profile is achieved using a high-energy implant after polysilicon gate definition. This simple process is accomplished through the utilization of very high-energy implants between 260 to 650 KeV. By implanting through the defined polysilicon gate using very high energy, a vertically engineered doping profile is achieved. In the channel region, the resulting implant peak is close to the surface while under the source-drain regions the implant peak is well below the junctions. The parasitic junction capacitance is less than that of a conventionally engineered device. Thus, performance of devices is increased through the reduction of parasitic junction capacitance. In this analysis an established 0.5 micrometers baseline technology shows a 10% reduction in the delay of a loaded inverter. Technologies with smaller or larger gate dimensions can be applied so well.
Local channel doping technology is another possibility for the reduction of parasitic capacitance. This process implants only on channel region of MOSFETs for the threshold voltage control and it suppresses any increase in well concentration under the source/drain region. A self-aligned counter-doped well process is published in IEEE Trans. Electron Devices, at page 1099 of vol. ED-43 on 1996. The title of this paper is "A Self-Aligned Counter-Doped Well Process Utilizing Channeling Ion Implantation". The authors of the paper described a new self-aligned counter-doped well process for low junction capacitance CMOS's. FIG. 1 according to the paper showed a concentration profile after channeling ion implantation and a lower net concentration in a well was resulted by counter well-doping technology. A process flow for manufacturing transistor devices was shown in FIG. 6. The self-aligned counter well doping was performed after the formation of gate and spacer. The conclusion of the paper was that a 50%-70% reduction in junction capacitance has been achieved by utilizing self-aligned counter doping of well with channeling ion implantation.
According to the above discussions, the prior art for reducing the source-drain parasitic capacitance is to perform a channel implantation after the formation of gate material. However, these two methods will cause a gate oxide reliability issue and need additional masks.